The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease.
Conventionally, techniques for forming the metal gate electrode can be cataloged as gate-first processes and gate-last processes. For a gate-first process, the metal gate electrode is formed before formation of source/drain regions of the transistors. The formation of the source/drain regions may include ion implantation processes and high-temperature thermal processes for annealing the implanted source/drain regions. During the high-temperature thermal process, the metal gate electrode is subjected to the high-temperature thermal process and is not thermally stable. To solve the problem, a gate-last process forms the source/drain regions within the substrate and a dummy gate within an interlayer dielectric (ILD). After the high temperature thermal process for annealing the source/drain regions, the dummy gate is removed and an opening is formed within the ILD. The metal gate electrode is then filled within the opening. Though the gate-last process may avoid the high temperature thermal process, the gate-last process is more complicate than the gate-first process.
Accordingly, transistor structures with metal gate electrodes and methods for forming the transistor structures are desired.